LL DMA Constants

channel

group DMA_LL_EC_CHANNEL

Defines

LL_DMA_CHANNEL_0 0x0001U

LL DMA channel 0

LL_DMA_CHANNEL_1 0x0002U

LL DMA channel 1

LL_DMA_CHANNEL_2 0x0004U

LL DMA channel 2

LL_DMA_CHANNEL_3 0x0008U

LL DMA channel 3

LL_DMA_CHANNEL_4 0x0010U

LL DMA channel 4

LL_DMA_CHANNEL_5 0x0020U

LL DMA channel 5

LL_DMA_CHANNEL_6 0x0040U

LL DMA channel 6

LL_DMA_CHANNEL_7 0x0080U

LL DMA channel 7

LL_DMA_CHANNEL_ALL 0x00FFU

LL DMA channel ALL

DMA channel instance

group DMA_LL_EC_DMA_CHANNEL_INSTANCE

Defines

LL_LPDMA1_CH0 LPDMA1_CH0

LL LPDMA1 channel 0

LL_LPDMA1_CH1 LPDMA1_CH1

LL LPDMA1 channel 1

LL_LPDMA1_CH2 LPDMA1_CH2

LL LPDMA1 channel 2

LL_LPDMA1_CH3 LPDMA1_CH3

LL LPDMA1 channel 3

LL_LPDMA1_CH4 LPDMA1_CH4

LL LPDMA1 channel 4

LL_LPDMA1_CH5 LPDMA1_CH5

LL LPDMA1 channel 5

LL_LPDMA1_CH6 LPDMA1_CH6

LL LPDMA1 channel 6

LL_LPDMA1_CH7 LPDMA1_CH7

LL LPDMA1 channel 7

LL_LPDMA2_CH0 LPDMA2_CH0

LL LPDMA2 channel 0

LL_LPDMA2_CH1 LPDMA2_CH1

LL LPDMA2 channel 1

LL_LPDMA2_CH2 LPDMA2_CH2

LL LPDMA2 channel 2

LL_LPDMA2_CH3 LPDMA2_CH3

LL LPDMA2 channel 3

DMA Interrupts

group DMA_LL_EC_INTERRUPTS

Defines

LL_DMA_IT_TC DMA_CCR_TCIE

Transfer complete interrupt

LL_DMA_IT_HT DMA_CCR_HTIE

Half transfer complete interrupt

LL_DMA_IT_DTE DMA_CCR_DTEIE

Data transfer error interrupt

LL_DMA_IT_ULE DMA_CCR_ULEIE

Update linked list item error interrupt

LL_DMA_IT_USE DMA_CCR_USEIE

User setting error interrupt

LL_DMA_IT_SUSP DMA_CCR_SUSPIE

Completed suspension interrupt

LL_DMA_IT_TO DMA_CCR_TOIE

Trigger overrun interrupt

LL_DMA_IT_ALL

(DMA_CCR_TCIE | DMA_CCR_HTIE | DMA_CCR_DTEIE | DMA_CCR_ULEIE | \

DMA_CCR_USEIE | DMA_CCR_SUSPIE | DMA_CCR_TOIE)


All interrupts

DMA Flags

group DMA_LL_EC_FLAGS

Defines

LL_DMA_FLAG_IDLE DMA_CSR_IDLEF

Idle flag

LL_DMA_FLAG_TC DMA_CSR_TCF

Transfer complete flag

LL_DMA_FLAG_HT DMA_CSR_HTF

Half transfer complete flag

LL_DMA_FLAG_DTE DMA_CSR_DTEF

Data transfer error flag

LL_DMA_FLAG_ULE DMA_CSR_ULEF

Update linked list item error flag

LL_DMA_FLAG_USE DMA_CSR_USEF

User setting error flag

LL_DMA_FLAG_SUSP DMA_CSR_SUSPF

Completed suspension flag

LL_DMA_FLAG_TO DMA_CSR_TOF

Trigger overrun flag

LL_DMA_FLAG_ALL

(DMA_CSR_TCF | DMA_CSR_HTF | DMA_CSR_DTEF | DMA_CSR_ULEF | \

DMA_CSR_USEF | DMA_CSR_SUSPF | DMA_CSR_TOF)


All flags

Priority Level

group DMA_LL_EC_PRIORITY_LEVEL

Defines

LL_DMA_PRIORITY_LOW_WEIGHT_LOW (0U)

Priority level : Low Priority, Low Weight

LL_DMA_PRIORITY_LOW_WEIGHT_MID DMA_CCR_PRIO_0

Priority level : Low Priority, Mid Weight

LL_DMA_PRIORITY_LOW_WEIGHT_HIGH DMA_CCR_PRIO_1

Priority level : Low Priority, High Weight

LL_DMA_PRIORITY_HIGH DMA_CCR_PRIO

Priority level : High Priority

Destination Increment Mode

group DMA_LL_EC_DESTINATION_INCREMENT_MODE

Defines

LL_DMA_DEST_ADDR_FIXED (0U)

Destination fixed single/burst

LL_DMA_DEST_ADDR_INCREMENTED DMA_CTR1_DINC

Destination incremented single/burst

Destination Data Width

group DMA_LL_EC_DESTINATION_DATA_WIDTH

Defines

LL_DMA_DEST_DATA_WIDTH_BYTE (0U)

Destination data width: byte

LL_DMA_DEST_DATA_WIDTH_HALFWORD DMA_CTR1_DDW_LOG2_0

Destination data width: halfword

LL_DMA_DEST_DATA_WIDTH_WORD DMA_CTR1_DDW_LOG2_1

Destination data width: word

Destination Data Truncation and Padding

group DMA_LL_EC_DESTINATION_DATA_TRUNCATION_PADDING

Defines

LL_DMA_DEST_DATA_TRUNC_LEFT_PADD_ZERO (0U)

If src data width < dest data width: => Right aligned, padded with 0 up to the destination data width. If src data width > dest data width: => Right aligned, left truncated down to the destination data width.

LL_DMA_DEST_DATA_TRUNC_RIGHT_PADD_SIGN DMA_CTR1_PAM_0

If src data width < dest data width: => Right aligned, padded with sign extended up to the destination data width. If src data width > dest data width: => Left aligned, right truncated down to the destination data width.

Source Increment Mode

group DMA_LL_EC_SOURCE_INCREMENT_MODE

Defines

LL_DMA_SRC_ADDR_FIXED (0U)

Source fixed single/burst

LL_DMA_SRC_ADDR_INCREMENTED DMA_CTR1_SINC

Source incremented single/burst

Source Data Width

group DMA_LL_EC_SOURCE_DATA_WIDTH

Defines

LL_DMA_SRC_DATA_WIDTH_BYTE (0U)

Source data width: byte

LL_DMA_SRC_DATA_WIDTH_HALFWORD DMA_CTR1_SDW_LOG2_0

Source data width: halfword

LL_DMA_SRC_DATA_WIDTH_WORD DMA_CTR1_SDW_LOG2_1

Source data width: word

Block Hardware Request

group DMA_LL_EC_BLKHW_REQUEST

Defines

LL_DMA_HARDWARE_REQUEST_BURST (0U)

Hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level

LL_DMA_HARDWARE_REQUEST_BLOCK DMA_CTR2_BREQ

Hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level

Transfer Event Mode

group DMA_LL_EC_TRANSFER_EVENT_MODE

Defines

LL_DMA_DIRECT_XFER_EVENT_BLOCK (0U)

The TC (and the HT) event is generated at the (respectively half of the) end of a block

LL_DMA_LINKEDLIST_XFER_EVENT_BLOCK LL_DMA_DIRECT_XFER_EVENT_BLOCK

The TC (and the HT) event is generated at the (respectively half of the) end of a block

LL_DMA_LINKEDLIST_XFER_EVENT_NODE DMA_CTR2_TCEM_1

The TC (and the HT) event is generated at the (respectively half) end of each linked list item

LL_DMA_LINKEDLIST_XFER_EVENT_Q DMA_CTR2_TCEM

The TC (and the HT) event is generated at the (respectively half) end of the last linked list item

Trigger Polarity

group DMA_LL_EC_TRIGGER_POLARITY

Defines

LL_DMA_TRIGGER_POLARITY_MASKED (0U)

No trigger of the selected DMA request. Masked trigger event

LL_DMA_TRIGGER_POLARITY_RISING DMA_CTR2_TRIGPOL_0

Trigger of the selected DMA request on the rising edge of the selected trigger event input

LL_DMA_TRIGGER_POLARITY_FALLING DMA_CTR2_TRIGPOL_1

Trigger of the selected DMA request on the falling edge of the selected trigger event input

Transfer Trigger Mode

group DMA_LL_EC_TRIGGER_MODE

Defines

LL_DMA_TRIGGER_BLOCK_TRANSFER (0U)

A block transfer is conditioned by (at least)one hit trigger

LL_DMA_TRIGGER_NODE_TRANSFER DMA_CTR2_TRIGM_1

A LLI link transfer is conditioned by (at least)one hit trigger

LL_DMA_TRIGGER_SINGLE_BURST_TRANSFER DMA_CTR2_TRIGM

A Single/Burst transfer is conditioned by (at least) one hit trigger

Flow Control Mode

group DMA_LL_EC_FLOW_CONTROL_MODE

Defines

LL_DMA_FLOW_CONTROL_DMA (0U)

Hardware request is driven by a peripheral with a hardware request/acknowledge protocol in DMA flow control mode

LL_DMA_FLOW_CONTROL_PERIPH DMA_CTR2_PFREQ

Hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral flow control mode

Transfer Direction

group DMA_LL_EC_TRANSFER_DIRECTION

Defines

LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CTR2_SWREQ

Memory to memory direction

LL_DMA_DIRECTION_PERIPH_TO_MEMORY (0U)

Peripheral to memory direction. Retained to ensure compatibility with other STM32.

LL_DMA_DIRECTION_MEMORY_TO_PERIPH LL_DMA_DIRECTION_PERIPH_TO_MEMORY

Memory to peripheral direction. Retained to ensure compatibility with other STM32.

Privilege Attribute

group DMA_LL_EC_PRIVILEGE_ATTRIBUTE

Defines

LL_DMA_ATTR_NPRIV (0U)

Non-privileged attribute

LL_DMA_ATTR_PRIV (1U)

Privileged attribute

Linked list register update

group DMA_LL_EC_LINKEDLIST_REGISTER_UPDATE

Defines

LL_DMA_UPDATE_CTR1 DMA_CLLR_UT1

Update CTR1 register from memory : available for all DMA channels

LL_DMA_UPDATE_CTR2 DMA_CLLR_UT2

Update CTR2 register from memory : available for all DMA channels

LL_DMA_UPDATE_CBR1 DMA_CLLR_UB1

Update CBR1 register from memory : available for all DMA channels

LL_DMA_UPDATE_CSAR DMA_CLLR_USA

Update CSAR register from memory : available for all DMA channels

LL_DMA_UPDATE_CDAR DMA_CLLR_UDA

Update CDAR register from memory : available for all DMA channels

LL_DMA_UPDATE_CLLR DMA_CLLR_ULL

Update CLLR register from memory : available for all DMA channels

LL_DMA_UPDATE_ALL

(DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | \

DMA_CLLR_UDA | DMA_CLLR_ULL)


Request Selection

group DMA_LL_EC_REQUEST_SELECTION

Defines

LL_LPDMA1_REQUEST_ADC1 0U

LPDMA1 HW Request is ADC1

LL_LPDMA1_REQUEST_ADC2 1U

LPDMA1 HW Request is ADC2

LL_LPDMA1_REQUEST_TIM6_UPD 2U

LPDMA1 HW Request is TIM6_UPD

LL_LPDMA1_REQUEST_TIM7_UPD 3U

LPDMA1 HW Request is TIM7_UPD

LL_LPDMA1_REQUEST_SPI1_RX 4U

LPDMA1 HW Request is SPI1_RX

LL_LPDMA1_REQUEST_SPI1_TX 5U

LPDMA1 HW Request is SPI1_TX

LL_LPDMA1_REQUEST_SPI2_RX 6U

LPDMA1 HW Request is SPI2_RX

LL_LPDMA1_REQUEST_SPI2_TX 7U

LPDMA1 HW Request is SPI2_TX

LL_LPDMA1_REQUEST_SPI3_RX 8U

LPDMA1 HW Request is SPI3_RX

LL_LPDMA1_REQUEST_SPI3_TX 9U

LPDMA1 HW Request is SPI3_TX

LL_LPDMA1_REQUEST_I2C1_RX 10U

LPDMA1 HW Request is I2C1_RX

LL_LPDMA1_REQUEST_I2C1_TX 11U

LPDMA1 HW Request is I2C1_TX

LL_LPDMA1_REQUEST_USART1_RX 12U

LPDMA1 HW Request is USART1_RX

LL_LPDMA1_REQUEST_USART1_TX 13U

LPDMA1 HW Request is USART1_TX

LL_LPDMA1_REQUEST_USART2_RX 14U

LPDMA1 HW Request is USART2_RX

LL_LPDMA1_REQUEST_USART2_TX 15U

LPDMA1 HW Request is USART2_TX

LL_LPDMA1_REQUEST_USART3_RX 16U

LPDMA1 HW Request is USART3_RX

LL_LPDMA1_REQUEST_USART3_TX 17U

LPDMA1 HW Request is USART3_TX

LL_LPDMA1_REQUEST_UART4_RX 18U

LPDMA1 HW Request is UART4_RX

LL_LPDMA1_REQUEST_UART4_TX 19U

LPDMA1 HW Request is UART4_TX

LL_LPDMA1_REQUEST_UART5_RX 20U

LPDMA1 HW Request is UART5_RX

LL_LPDMA1_REQUEST_UART5_TX 21U

LPDMA1 HW Request is UART5_TX

LL_LPDMA1_REQUEST_LPUART1_RX 22U

LPDMA1 HW Request is LPUART1_RX

LL_LPDMA1_REQUEST_LPUART1_TX 23U

LPDMA1 HW Request is LPUART1_TX

LL_LPDMA1_REQUEST_TIM1_CC1 24U

LPDMA1 HW Request is TIM1_CC1

LL_LPDMA1_REQUEST_TIM1_CC2 25U

LPDMA1 HW Request is TIM1_CC2

LL_LPDMA1_REQUEST_TIM1_CC3 26U

LPDMA1 HW Request is TIM1_CC3

LL_LPDMA1_REQUEST_TIM1_CC4 27U

LPDMA1 HW Request is TIM1_CC4

LL_LPDMA1_REQUEST_TIM1_UPD 28U

LPDMA1 HW Request is TIM1_UPD

LL_LPDMA1_REQUEST_TIM1_TRGI 29U

LPDMA1 HW Request is TIM1_TRGI

LL_LPDMA1_REQUEST_TIM1_COM 30U

LPDMA1 HW Request is TIM1_COM

LL_LPDMA1_REQUEST_TIM2_CC1 31U

LPDMA1 HW Request is TIM2_CC1

LL_LPDMA1_REQUEST_TIM2_CC2 32U

LPDMA1 HW Request is TIM2_CC2

LL_LPDMA1_REQUEST_TIM2_CC3 33U

LPDMA1 HW Request is TIM2_CC3

LL_LPDMA1_REQUEST_TIM2_CC4 34U

LPDMA1 HW Request is TIM2_CC4

LL_LPDMA1_REQUEST_TIM2_UPD 35U

LPDMA1 HW Request is TIM2_UPD

LL_LPDMA1_REQUEST_TIM2_TRGI 36U

LPDMA1 HW Request is TIM2_TRGI

LL_LPDMA1_REQUEST_TIM5_CC1 37U

LPDMA1 HW Request is TIM5_CC1

LL_LPDMA1_REQUEST_TIM5_CC2 38U

LPDMA1 HW Request is TIM5_CC2

LL_LPDMA1_REQUEST_TIM5_CC3 39U

LPDMA1 HW Request is TIM5_CC3

LL_LPDMA1_REQUEST_TIM5_CC4 40U

LPDMA1 HW Request is TIM5_CC4

LL_LPDMA1_REQUEST_TIM5_UPD 41U

LPDMA1 HW Request is TIM5_UPD

LL_LPDMA1_REQUEST_TIM5_TRGI 42U

LPDMA1 HW Request is TIM5_TRGI

LL_LPDMA1_REQUEST_TIM15_CC1 43U

LPDMA1 HW Request is TIM15_CC1

LL_LPDMA1_REQUEST_TIM15_CC2 44U

LPDMA1 HW Request is TIM15_CC2

LL_LPDMA1_REQUEST_TIM15_UPD 45U

LPDMA1 HW Request is TIM15_UPD

LL_LPDMA1_REQUEST_TIM15_TRGI 46U

LPDMA1 HW Request is TIM15_TRGI

LL_LPDMA1_REQUEST_TIM15_COM 47U

LPDMA1 HW Request is TIM15_COM

LL_LPDMA1_REQUEST_TIM16_CC1 48U

LPDMA1 HW Request is TIM16_CC1

LL_LPDMA1_REQUEST_TIM16_UPD 49U

LPDMA1 HW Request is TIM16_UPD

LL_LPDMA1_REQUEST_TIM17_CC1 50U

LPDMA1 HW Request is TIM17_CC1

LL_LPDMA1_REQUEST_TIM17_UPD 51U

LPDMA1 HW Request is TIM17_UPD

LL_LPDMA1_REQUEST_LPTIM1_IC1 52U

LPDMA1 HW Request is LPTIM1_IC1

LL_LPDMA1_REQUEST_LPTIM1_IC2 53U

LPDMA1 HW Request is LPTIM1_IC2

LL_LPDMA1_REQUEST_LPTIM1_UE 54U

LPDMA1 HW Request is LPTIM1_UE

LL_LPDMA1_REQUEST_CORDIC_RD 55U

LPDMA1 HW Request is CORDIC_RD

LL_LPDMA1_REQUEST_CORDIC_WR 56U

LPDMA1 HW Request is CORDIC_WR

LL_LPDMA1_REQUEST_I3C1_RX 57U

LPDMA1 HW Request is I3C1_RX

LL_LPDMA1_REQUEST_I3C1_TX 58U

LPDMA1 HW Request is I3C1_TX

LL_LPDMA1_REQUEST_I3C1_TC 59U

LPDMA1 HW Request is I3C1_TC

LL_LPDMA1_REQUEST_I3C1_RS 60U

LPDMA1 HW Request is I3C1_RS

LL_LPDMA1_REQUEST_AES_OUT 61U

LPDMA1 HW Request is AES_OUT

LL_LPDMA1_REQUEST_AES_IN 62U

LPDMA1 HW Request is AES_IN

LL_LPDMA1_REQUEST_HASH_IN 63U

LPDMA1 HW Request is HASH_IN

LL_LPDMA1_REQUEST_I2C2_RX 64U

LPDMA1 HW Request is I2C2_RX

LL_LPDMA1_REQUEST_I2C2_TX 65U

LPDMA1 HW Request is I2C2_TX

LL_LPDMA1_REQUEST_TIM8_CC1 66U

LPDMA1 HW Request is TIM8_CC1

LL_LPDMA1_REQUEST_TIM8_CC2 67U

LPDMA1 HW Request is TIM8_CC2

LL_LPDMA1_REQUEST_TIM8_CC3 68U

LPDMA1 HW Request is TIM8_CC3

LL_LPDMA1_REQUEST_TIM8_CC4 69U

LPDMA1 HW Request is TIM8_CC4

LL_LPDMA1_REQUEST_TIM8_UPD 70U

LPDMA1 HW Request is TIM8_UPD

LL_LPDMA1_REQUEST_TIM8_TRGI 71U

LPDMA1 HW Request is TIM8_TRGI

LL_LPDMA1_REQUEST_TIM8_COM 72U

LPDMA1 HW Request is TIM8_COM

LL_LPDMA1_REQUEST_DAC1_CH1 73U

LPDMA1 HW Request is DAC1_CH1

LL_LPDMA2_REQUEST_ADC1 0U

LPDMA2 HW Request is ADC1

LL_LPDMA2_REQUEST_ADC2 1U

LPDMA2 HW Request is ADC2

LL_LPDMA2_REQUEST_TIM6_UPD 2U

LPDMA2 HW Request is TIM6_UPD

LL_LPDMA2_REQUEST_TIM7_UPD 3U

LPDMA2 HW Request is TIM7_UPD

LL_LPDMA2_REQUEST_SPI2S1_RX 4U

LPDMA2 HW Request is SPI2S1_RX

LL_LPDMA2_REQUEST_SPI1_RX 4U

LPDMA2 HW Request is SPI1_RX

LL_LPDMA2_REQUEST_SPI1_TX 5U

LPDMA2 HW Request is SPI1_TX

LL_LPDMA2_REQUEST_SPI2_RX 6U

LPDMA2 HW Request is SPI2_RX

LL_LPDMA2_REQUEST_SPI2_TX 7U

LPDMA2 HW Request is SPI2_TX

LL_LPDMA2_REQUEST_SPI3_RX 8U

LPDMA2 HW Request is SPI3_RX

LL_LPDMA2_REQUEST_SPI3_TX 9U

LPDMA2 HW Request is SPI3_TX

LL_LPDMA2_REQUEST_I2C1_RX 10U

LPDMA2 HW Request is I2C1_RX

LL_LPDMA2_REQUEST_I2C1_TX 11U

LPDMA2 HW Request is I2C1_TX

LL_LPDMA2_REQUEST_USART1_RX 12U

LPDMA2 HW Request is USART1_RX

LL_LPDMA2_REQUEST_USART1_TX 13U

LPDMA2 HW Request is USART1_TX

LL_LPDMA2_REQUEST_USART2_RX 14U

LPDMA2 HW Request is USART2_RX

LL_LPDMA2_REQUEST_USART2_TX 15U

LPDMA2 HW Request is USART2_TX

LL_LPDMA2_REQUEST_USART3_RX 16U

LPDMA2 HW Request is USART3_RX

LL_LPDMA2_REQUEST_USART3_TX 17U

LPDMA2 HW Request is USART3_TX

LL_LPDMA2_REQUEST_UART4_RX 18U

LPDMA2 HW Request is UART4_RX

LL_LPDMA2_REQUEST_UART4_TX 19U

LPDMA2 HW Request is UART4_TX

LL_LPDMA2_REQUEST_UART5_RX 20U

LPDMA2 HW Request is UART5_RX

LL_LPDMA2_REQUEST_UART5_TX 21U

LPDMA2 HW Request is UART5_TX

LL_LPDMA2_REQUEST_LPUART1_RX 22U

LPDMA2 HW Request is LPUART1_RX

LL_LPDMA2_REQUEST_LPUART1_TX 23U

LPDMA2 HW Request is LPUART1_TX

LL_LPDMA2_REQUEST_TIM1_CC1 24U

LPDMA2 HW Request is TIM1_CC1

LL_LPDMA2_REQUEST_TIM1_CC2 25U

LPDMA2 HW Request is TIM1_CC2

LL_LPDMA2_REQUEST_TIM1_CC3 26U

LPDMA2 HW Request is TIM1_CC3

LL_LPDMA2_REQUEST_TIM1_CC4 27U

LPDMA2 HW Request is TIM1_CC4

LL_LPDMA2_REQUEST_TIM1_UPD 28U

LPDMA2 HW Request is TIM1_UPD

LL_LPDMA2_REQUEST_TIM1_TRGI 29U

LPDMA2 HW Request is TIM1_TRGI

LL_LPDMA2_REQUEST_TIM1_COM 30U

LPDMA2 HW Request is TIM1_COM

LL_LPDMA2_REQUEST_TIM2_CC1 31U

LPDMA2 HW Request is TIM2_CC1

LL_LPDMA2_REQUEST_TIM2_CC2 32U

LPDMA2 HW Request is TIM2_CC2

LL_LPDMA2_REQUEST_TIM2_CC3 33U

LPDMA2 HW Request is TIM2_CC3

LL_LPDMA2_REQUEST_TIM2_CC4 34U

LPDMA2 HW Request is TIM2_CC4

LL_LPDMA2_REQUEST_TIM2_UPD 35U

LPDMA2 HW Request is TIM2_UPD

LL_LPDMA2_REQUEST_TIM2_TRGI 36U

LPDMA2 HW Request is TIM2_TRGI

LL_LPDMA2_REQUEST_TIM5_CC1 37U

LPDMA2 HW Request is TIM5_CC1

LL_LPDMA2_REQUEST_TIM5_CC2 38U

LPDMA2 HW Request is TIM5_CC2

LL_LPDMA2_REQUEST_TIM5_CC3 39U

LPDMA2 HW Request is TIM5_CC3

LL_LPDMA2_REQUEST_TIM5_CC4 40U

LPDMA2 HW Request is TIM5_CC4

LL_LPDMA2_REQUEST_TIM5_UPD 41U

LPDMA2 HW Request is TIM5_UPD

LL_LPDMA2_REQUEST_TIM5_TRGI 42U

LPDMA2 HW Request is TIM5_TRGI

LL_LPDMA2_REQUEST_TIM15_CC1 43U

LPDMA2 HW Request is TIM15_CC1

LL_LPDMA2_REQUEST_TIM15_CC2 44U

LPDMA2 HW Request is TIM15_CC2

LL_LPDMA2_REQUEST_TIM15_UPD 45U

LPDMA2 HW Request is TIM15_UPD

LL_LPDMA2_REQUEST_TIM15_TRGI 46U

LPDMA2 HW Request is TIM15_TRGI

LL_LPDMA2_REQUEST_TIM15_COM 47U

LPDMA2 HW Request is TIM15_COM

LL_LPDMA2_REQUEST_TIM16_CC1 48U

LPDMA2 HW Request is TIM16_CC1

LL_LPDMA2_REQUEST_TIM16_UPD 49U

LPDMA2 HW Request is TIM16_UPD

LL_LPDMA2_REQUEST_TIM17_CC1 50U

LPDMA2 HW Request is TIM17_CC1

LL_LPDMA2_REQUEST_TIM17_UPD 51U

LPDMA2 HW Request is TIM17_UPD

LL_LPDMA2_REQUEST_LPTIM1_IC1 52U

LPDMA2 HW Request is LPTIM1_IC1

LL_LPDMA2_REQUEST_LPTIM1_IC2 53U

LPDMA2 HW Request is LPTIM1_IC2

LL_LPDMA2_REQUEST_LPTIM1_UE 54U

LPDMA2 HW Request is LPTIM1_UE

LL_LPDMA2_REQUEST_CORDIC_RD 55U

LPDMA2 HW Request is CORDIC_RD

LL_LPDMA2_REQUEST_CORDIC_WR 56U

LPDMA2 HW Request is CORDIC_WR

LL_LPDMA2_REQUEST_I3C1_RX 57U

LPDMA2 HW Request is I3C1_RX

LL_LPDMA2_REQUEST_I3C1_TX 58U

LPDMA2 HW Request is I3C1_TX

LL_LPDMA2_REQUEST_I3C1_TC 59U

LPDMA2 HW Request is I3C1_TC

LL_LPDMA2_REQUEST_I3C1_RS 60U

LPDMA2 HW Request is I3C1_RS

LL_LPDMA2_REQUEST_AES_OUT 61U

LPDMA2 HW Request is AES_OUT

LL_LPDMA2_REQUEST_AES_IN 62U

LPDMA2 HW Request is AES_IN

LL_LPDMA2_REQUEST_HASH_IN 63U

LPDMA2 HW Request is HASH_IN

LL_LPDMA2_REQUEST_I2C2_RX 64U

LPDMA2 HW Request is I2C2_RX

LL_LPDMA2_REQUEST_I2C2_TX 65U

LPDMA2 HW Request is I2C2_TX

LL_LPDMA2_REQUEST_TIM8_CC1 66U

LPDMA2 HW Request is TIM8_CC1

LL_LPDMA2_REQUEST_TIM8_CC2 67U

LPDMA2 HW Request is TIM8_CC2

LL_LPDMA2_REQUEST_TIM8_CC3 68U

LPDMA2 HW Request is TIM8_CC3

LL_LPDMA2_REQUEST_TIM8_CC4 69U

LPDMA2 HW Request is TIM8_CC4

LL_LPDMA2_REQUEST_TIM8_UPD 70U

LPDMA2 HW Request is TIM8_UPD

LL_LPDMA2_REQUEST_TIM8_TRGI 71U

LPDMA2 HW Request is TIM8_TRGI

LL_LPDMA2_REQUEST_TIM8_COM 72U

LPDMA2 HW Request is TIM8_COM

LL_LPDMA2_REQUEST_DAC1_CH1 73U

LPDMA2 HW Request is DAC1_CH1

Trigger Selection

group DMA_LL_EC_TRIGGER_SELECTION

Defines

LL_LPDMA1_TRIGGER_EXTI0 0U

LPDMA1 HW Trigger is EXTI0

LL_LPDMA1_TRIGGER_EXTI1 1U

LPDMA1 HW Trigger is EXTI1

LL_LPDMA1_TRIGGER_EXTI2 2U

LPDMA1 HW Trigger is EXTI2

LL_LPDMA1_TRIGGER_EXTI3 3U

LPDMA1 HW Trigger is EXTI3

LL_LPDMA1_TRIGGER_EXTI4 4U

LPDMA1 HW Trigger is EXTI4

LL_LPDMA1_TRIGGER_EXTI5 5U

LPDMA1 HW Trigger is EXTI5

LL_LPDMA1_TRIGGER_EXTI6 6U

LPDMA1 HW Trigger is EXTI6

LL_LPDMA1_TRIGGER_EXTI7 7U

LPDMA1 HW Trigger is EXTI7

LL_LPDMA1_TRIGGER_TAMP_TRG1 8U

LPDMA1 HW Trigger is TAMP_TRG1

LL_LPDMA1_TRIGGER_TAMP_TRG2 9U

LPDMA1 HW Trigger is TAMP_TRG2

LL_LPDMA1_TRIGGER_TAMP_TRG3 10U

LPDMA1 HW Trigger is TAMP_TRG3

LL_LPDMA1_TRIGGER_LPTIM1_CH1 11U

LPDMA1 HW Trigger is LPTIM1_CH1

LL_LPDMA1_TRIGGER_LPTIM1_CH2 12U

LPDMA1 HW Trigger is LPTIM1_CH2

LL_LPDMA1_TRIGGER_RTC_ALRA_TRG 13U

LPDMA1 HW Trigger is RTC_ALRA_TRG

LL_LPDMA1_TRIGGER_RTC_ALRB_TRG 14U

LPDMA1 HW Trigger is RTC_ALRB_TRG

LL_LPDMA1_TRIGGER_RTC_WUT_TRG 15U

LPDMA1 HW Trigger is RTC_WUT_TRG

LL_LPDMA1_TRIGGER_TIM2_TRGO 16U

LPDMA1 HW Trigger is TIM2_TRGO

LL_LPDMA1_TRIGGER_TIM15_TRGO 17U

LPDMA1 HW Trigger is TIM15_TRGO

LL_LPDMA1_TRIGGER_COMP1_OUT 18U

LPDMA1 HW Trigger is COMP1_OUT

LL_LPDMA1_TRIGGER_EVENTOUT 19U

LPDMA1 HW Trigger is EVENTOUT

LL_LPDMA1_TRIGGER_LPDMA1_CH0_TC 20U

LPDMA1 HW Trigger is LPDMA1_CH0_TC

LL_LPDMA1_TRIGGER_LPDMA1_CH1_TC 21U

LPDMA1 HW Trigger is LPDMA1_CH1_TC

LL_LPDMA1_TRIGGER_LPDMA1_CH2_TC 22U

LPDMA1 HW Trigger is LPDMA1_CH2_TC

LL_LPDMA1_TRIGGER_LPDMA1_CH3_TC 23U

LPDMA1 HW Trigger is LPDMA1_CH3_TC

LL_LPDMA1_TRIGGER_LPDMA1_CH4_TC 24U

LPDMA1 HW Trigger is LPDMA1_CH4_TC

LL_LPDMA1_TRIGGER_LPDMA1_CH5_TC 25U

LPDMA1 HW Trigger is LPDMA1_CH5_TC

LL_LPDMA1_TRIGGER_LPDMA1_CH6_TC 26U

LPDMA1 HW Trigger is LPDMA1_CH6_TC

LL_LPDMA1_TRIGGER_LPDMA1_CH7_TC 27U

LPDMA1 HW Trigger is LPDMA1_CH7_TC

LL_LPDMA1_TRIGGER_LPDMA2_CH0_TC 28U

LPDMA1 HW Trigger is LPDMA2_CH0_TC

LL_LPDMA1_TRIGGER_LPDMA2_CH1_TC 29U

LPDMA1 HW Trigger is LPDMA2_CH1_TC

LL_LPDMA1_TRIGGER_LPDMA2_CH2_TC 30U

LPDMA1 HW Trigger is LPDMA2_CH2_TC

LL_LPDMA1_TRIGGER_LPDMA2_CH3_TC 31U

LPDMA1 HW Trigger is LPDMA2_CH3_TC

LL_LPDMA2_TRIGGER_EXTI0 0U

LPDMA2 HW Trigger is EXTI0

LL_LPDMA2_TRIGGER_EXTI1 1U

LPDMA2 HW Trigger is EXTI1

LL_LPDMA2_TRIGGER_EXTI2 2U

LPDMA2 HW Trigger is EXTI2

LL_LPDMA2_TRIGGER_EXTI3 3U

LPDMA2 HW Trigger is EXTI3

LL_LPDMA2_TRIGGER_EXTI4 4U

LPDMA2 HW Trigger is EXTI4

LL_LPDMA2_TRIGGER_EXTI5 5U

LPDMA2 HW Trigger is EXTI5

LL_LPDMA2_TRIGGER_EXTI6 6U

LPDMA2 HW Trigger is EXTI6

LL_LPDMA2_TRIGGER_EXTI7 7U

LPDMA2 HW Trigger is EXTI7

LL_LPDMA2_TRIGGER_TAMP_TRG1 8U

LPDMA2 HW Trigger is TAMP_TRG1

LL_LPDMA2_TRIGGER_TAMP_TRG2 9U

LPDMA2 HW Trigger is TAMP_TRG2

LL_LPDMA2_TRIGGER_TAMP_TRG3 10U

LPDMA2 HW Trigger is TAMP_TRG3

LL_LPDMA2_TRIGGER_LPTIM1_CH1 11U

LPDMA2 HW Trigger is LPTIM1_CH1

LL_LPDMA2_TRIGGER_LPTIM1_CH2 12U

LPDMA2 HW Trigger is LPTIM1_CH2

LL_LPDMA2_TRIGGER_RTC_ALRA_TRG 13U

LPDMA2 HW Trigger is RTC_ALRA_TRG

LL_LPDMA2_TRIGGER_RTC_ALRB_TRG 14U

LPDMA2 HW Trigger is RTC_ALRB_TRG

LL_LPDMA2_TRIGGER_RTC_WUT_TRG 15U

LPDMA2 HW Trigger is RTC_WUT_TRG

LL_LPDMA2_TRIGGER_TIM2_TRGO 16U

LPDMA2 HW Trigger is TIM2_TRGO

LL_LPDMA2_TRIGGER_TIM15_TRGO 17U

LPDMA2 HW Trigger is TIM15_TRGO

LL_LPDMA2_TRIGGER_COMP1_OUT 18U

LPDMA2 HW Trigger is COMP1_OUT

LL_LPDMA2_TRIGGER_EVENTOUT 19U

LPDMA2 HW Trigger is EVENTOUT

LL_LPDMA2_TRIGGER_LPDMA1_CH0_TC 20U

LPDMA2 HW Trigger is LPDMA1_CH0_TC

LL_LPDMA2_TRIGGER_LPDMA1_CH1_TC 21U

LPDMA2 HW Trigger is LPDMA1_CH1_TC

LL_LPDMA2_TRIGGER_LPDMA1_CH2_TC 22U

LPDMA2 HW Trigger is LPDMA1_CH2_TC

LL_LPDMA2_TRIGGER_LPDMA1_CH3_TC 23U

LPDMA2 HW Trigger is LPDMA1_CH3_TC

LL_LPDMA2_TRIGGER_LPDMA1_CH4_TC 24U

LPDMA2 HW Trigger is LPDMA1_CH4_TC

LL_LPDMA2_TRIGGER_LPDMA1_CH5_TC 25U

LPDMA2 HW Trigger is LPDMA1_CH5_TC

LL_LPDMA2_TRIGGER_LPDMA1_CH6_TC 26U

LPDMA2 HW Trigger is LPDMA1_CH6_TC

LL_LPDMA2_TRIGGER_LPDMA1_CH7_TC 27U

LPDMA2 HW Trigger is LPDMA1_CH7_TC

LL_LPDMA2_TRIGGER_LPDMA2_CH0_TC 28U

LPDMA2 HW Trigger is LPDMA2_CH0_TC

LL_LPDMA2_TRIGGER_LPDMA2_CH1_TC 29U

LPDMA2 HW Trigger is LPDMA2_CH1_TC

LL_LPDMA2_TRIGGER_LPDMA2_CH2_TC 30U

LPDMA2 HW Trigger is LPDMA2_CH2_TC

LL_LPDMA2_TRIGGER_LPDMA2_CH3_TC 31U

LPDMA2 HW Trigger is LPDMA2_CH3_TC